1. Field of the Invention
This invention relates to an improved EXCLUSIVE-NOR circuit and, more particularly, to a control circuit which uses an EXCLUSIVE-NOR circuit to aid in selection of a read-only memory ROM or a random-access memory RAM array.
2. Prior Art
Previously, integrated circuits have included both ROM arrays and RAM arrays on the same chip. In order to select the ROM array, a ROM SELECT signal (ROMCS*) is provided which is active when LOW. In order to select the RAM array, a RAM SELECT signal (RAMCS*) is provided which is active when LOW. When different addresses are used for either the RAM array or the ROM array, an address transition detector (ATD) circuit is used to start respective streams of pulses required for operation of either the RAM or ROM arrays. These pulses, for example, precharge the bit lines, turn on sense amplifiers, and enable output buffers.
However, in the case where the same address is used for both the RAM array and the ROM array, there is no address transition to activate the ATD circuit and start the stream of required pulses for a ROM or RAM array. For this situation, prior art circuits modify the ATD circuit so that the ATD circuit reacts to a chip enable signal (CE), where the CE signal is derived from the RAM SELECT signal (RAMCS*) or the ROM SELECT signal (ROMCS*) and CE is normally LOW and active HIGH. CE=1, or is HIGH, when either the RAMCS* signal or the ROMCS* signal is active LOW.
In the situation where the chip is switching operation from the RAM to the ROM occurs or vice-versa, the CE signal is required to go LOW and then to go HIGH. This requires that the RAMCS* signal and the ROMCS* signal both be off momentarily, or HIGH.
However, a problem arises in the situation where both arrays are turned on in the situation where either the ROM is turned on before turning off the RAM or else the RAM is turned on before turning off the ROM. In either case, the CE signal never goes LOW, as is required to activate the ATD circuit. In this case, the CE signal just stays HIGH so that the ATD circuit is not activated to initiate the required pulses for proper operation of the RAM or ROM array. A solution to this problem is to use an XNOR circuit in a CE buffer circuit so that whenever the ROMCS* and the RAMCS* signals are the same, CE goes LOW.
However, a problem arises with using the XNOR circuit because the XNOR circuit does not react instantaneously when the ROM and RAM arrays are simultaneously switched. There is a time interval centered about the simultaneous switching time during which time interval the XNOR circuit does not function as required.
Consequently a need exists for improvement to the operation of the XNOR circuit so that a CE signal is provided to activate the ATD circuit even when the ROM and RAM are switched simultaneously.